1. Field of the Invention
The present invention relates to flash memory arrays. More particularly, the present invention relates to an internal refresh mode in a flash memory array.
2. The Prior Art
In a typical flash memory array, the memory cells are arranged in a rectangular array of rows and columns. Portions of a conventional flash memory array 10 are depicted in FIG. 1. In the flash memory array 10, wordlines 12 and bitlines 14 are arranged as a matrix to form intersections that have flash memory cells 16 disposed therein. A known flash memory cell suitable for use according to the present invention is described in U.S. Pat. No. 4,783,766, filed May 30, 1986, assigned to the same assignee as the present invention, and incorporated herein by reference.
Each wordline 12 in the flash memory array 10 represents one of M rows, wherein each of the M rows has N words. Each of the M rows in the flash memory array 10 is typically referred to as a page of memory. The number of bitlines 14 in the flash memory array 10 is approximately the same as the number of N words in a row multiplied by the number of bits in each word. For example, in the 4-Megabit Serial DataFlash.TM., part number AT45DB041, by Atmel Corporation, San Jose, Calif., each row of a known 4M flash memory array 10, there are 264 words each having 8 bits.
For each of the flash memory elements disposed at the intersection of a wordline 12 and a bit line 14, the drain of the flash memory element 16 is connected to the bit line 14, the source of the flash memory element 16 is connected to an array source voltage by an array source line 20, and the gate of the flash memory element 16 is connected to the word line 12. For each of the word lines 12, a P-channel MOS isolation pass transistor 22 is connected in series between wordline access circuitry (not shown) and the first flash memory element 16 disposed at the intersection of the wordline 12 and a bit line 14. Connected to the portion of each word line 12 disposed between P-channel MOS isolation pass transistor 22 and the gate of the first flash memory element 16 in each row is a word line pump 24 connected to a source of negative voltage during erase of about -15 volts to about -4 volts, and preferably -10 volts, by word line negative pump line 26.
The operations that may be performed on the memory cells in the flash memory array are PROGRAM, ERASE and READ. The PROGRAM operation is often performed by driving selected bitlines 14 connected to the drain region in the flash memory cells 16 to a first voltage and driving the gates of the flash memory cells 16 connected to selected wordlines 12 to a second higher voltage to perform hot electron injection in a manner well known to those of ordinary skill in the art.
The ERASE operation is performed by driving the gate of the flash memory cell 16 to a voltage that is substantially less than a voltage placed on the bitline 14. In doing so, electrons are tunneled off of the floating gate of the flash memory cell 16 in a manner well known to those of ordinary skill in the art. For a conventional flash memory array 10, it is known that ERASE operation may be a BULK ERASE wherein the entire flash memory array 10 is erased, a SECTOR ERASE wherein a sector in the flash memory array 10 is erased, or a PAGE ERASE wherein an erase may be performed on a single row in a sector. By constraining the ERASE operation to either a SECTOR or BULK ERASE, the disturb phenomenon associated with the occurrence of unintended tunneling in unselected rows is reduced.
Although the erase disturb phenomenon can be reduced by the manner in which the ERASE operation is performed, an external refresh of the memory cells may be performed as described in the data sheet for the Atmel 4-Megabit Serial Dataflash.TM. part no. AT45DB041 for disturbs cause by both erase and program operations. In the external refresh an Auto Page Rewrite command may be employed by the data flash user to refresh a row in the flash memory array by reading the data stored in the row into a buffer, and then writing the data stored in the buffer back into the same row. The Auto Page Rewrite command describing the buffer write operation is further disclosed in U.S. patent application Ser. No. 08/824,175 to Gupta et al., filed Mar. 26, 1997, entitled "Dual Buffer Flash Memory Architecture With Multiple Operating Modes", assigned to the same assignee as the present application, and expressly incorporated herein by reference. Performing the external refresh with the Auto Page Rewrite command requires the user of the flash memory array to provide the instructions for performing the Auto Page Rewrite and also to provide a sequentially incremented page address for row to be refreshed. Requiring the user to provide these instructions may at times prove to be cumbersome to the user of the flash memory array.
It is therefore an object of the present invention to provide an internal row refresh for a flash memory array that automatically scrolls through the rows in a flash memory array to refresh the memory cells of the flash memory array.
It is a further object of the present invention to provide an internal row refresh for a flash memory array that is programmable by the user to automatically scroll through the rows in a flash memory array to refresh one row of the memory cells after every Nth erase and program operation of the flash memory array.